NASA has selected SiFive, an American chip startup that designs RISC-V CPUs, to provide the “core CPU” for the space agency’s upcoming High Performance Spacecraft (HPSC) processor. pillar.
NASA announced in June that its HPSC project will develop new flying plane technology capable of computing “at least 100 times” than current spacecraft computers, developed nearly 30 years ago.
These CPUs need to be able to resist radiation damage, operate at minimal power and turn off when not needed, but still be capable of robotic landing on Mars and supporting astronauts in space. time.
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The main problem with older spacecraft is that they are over-engineered, built for the most computationally demanding parts of a mission, such as during a Mars landing sequence. They also need to operate with minimal power.
Engineers from NASA’s Jet Propulsion Laboratory (JPL) are leading the development of the HPSC to provide its multi-core chips and operating software. HPSC has to process data 100 times faster than current ‘spatial qualified’ computers because of power constraints.
According to SiFiveNASA’s HPSC will use an 8-core SiFive ‘Intelligence’ X280 RISC-V vector core and four additional SiFive RISC-V cores.
The chip designer says the X280 has demonstrated the 100x speedup required for NASA’s HSPC and is suitable for applications that require high throughput, single-threaded performance in power-constrained conditions. .
“The X280 represents orders of magnitude more performance than competitive microprocessor technology, and our SiFive RISC-V IP allows NASA to leverage support, flexibility, and long-term viability of the rapidly growing global RISC-V ecosystem” speak Jack Kang, SVP of business development at SiFive.
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NASA’s selection of SiFive is a small but significant victory over the open source standard RISC-V (pronounced “risk-year”), invented by University of California professors David Patterson and Krste Asanović Berkeley 12 years ago.
Developers are free to change the instruction set architecture (ISA) of the RISC-V chip, which defines how the chip hardware works. This sets it apart from Intel’s x86 closed ISA, which dominates PCs and servers, and ARM instructions licensed by ARM Ltd to most smartphone manufacturers and that have become commonplace. for Apple’s M1 chip for Macs.
Per a reported from The Register in MayRISC-V International director Calista Redmond said a RISC-V laptop will be revealed this year.
SiFive in March raised $175 million, valued it at $2.5 billion. To date, it has raised more than $350 million from investors including Intel Capital, SK Hynix, and Qualcomm Ventures.
Intel also sees some opportunities in RISC-V chips following the launch of Intel Foundry Services (IFS) last year and its return to making chips for others. In February, Intel join RISC-V as a top member and, with IFS, announced a $1 billion fund to enhance tools for ISA on x86, Arm, and RISC-V. And it’s doing High-performance RISC-V cores from the Ventana Microcro chip starter available through IFS.
NASA JPL in August announced they have selected US-based industrial embedded control system developer Microchip Technology to develop its HPSC processor. Microchip Technology was contracted to architect, design and supply HPSC processors for 3 years under a $50 million contract. NASA’s announcement does not mention RISC-V but Microchip in June announced The industry’s first RISC-based field-programmable gate array (FPGA) based on RISC-V.
According to Microchip, its design will provide “comprehensive Ethernet networking, advanced artificial intelligence/machine learning processing, and connectivity support” for NASA.
